The present invention relates to a data processing circuit having a plurality of elements, wherein said elements operate in response to coded instructions while receiving clocking signals.
Data processing environments are known in which elements operate in response to decoded instructions while receiving clocking signals. A clocking signal is often generated by a quartz oscillator or similar and the signals are distributed throughout the circuit so as to provide a common reference for manipulations performed within the elements. The overall processing speed of a device may be increased by increasing the frequency of the clock although an upper bound will be reached beyond which satisfactory operation is not possible. Furthermore, the clocking of elements within a circuit also results in power dissipation which is an important factor when considering apparatus driven by a limited power supply, such as that provided by a battery.
A known approach towards reducing power consumption is to effectively stop the operation of the clock when processing within the circuit is not required. The chip is said to be placed in its idle mode and additional components are required in order to selectively place the circuit in one of its operational modes; that is in its active power dissipating mode or its reduced power dissipation idle mode. A problem with this approach is that the stopping of the clock results in a total shut down of the circuit therefore periods during which the clock may actually be stopped are limited and the power saving may be off-set by the additional measures that must be taken when selecting periods of shut down.